Current Issue : January - March Volume : 2018 Issue Number : 1 Articles : 5 Articles
Sensors play the most important role in observing changes in an environment they are a\npart. They detect even the smallest changes and send the information to other electronic devices.\nMaking sure that these sensors provide an accurate output is equally crucial, as the data it measures\nand collects are used for analysis. Until now, calibrating sensors has been done manually by following\na sequence of procedures, and is usually performed on-site or in a laboratory prior to deployment.\nTo eliminate the manual procedure in the calibration (at the very least), an ion-sensitive field-effect\ntransistor (ISFET) with a built-in calibration registers circuit was created through segmented eight-bit\nbinary search in a three-point algorithm using a field-programmable gate array (FPGA). The circuit\nwas created using a three-point calibration algorithm and three standard buffers (pH 4, pH 7,\nand pH 10). The block diagram, schematic diagram, and the number of logic gates were derived after\nsynthesizing the Verilog program in Xilinx/FPGA. An average of 0.30% error was computed to prove\nthe reliability of the created circuit using FPGA. Having an ISFET with built-in calibration registers\nwill alleviate the work of experts in performing calibrations. This would follow the plug and play\nstandard, hence its being a calibration-ready ISFET device. With this feature, it could be used as a pH\nlevel meter or a remote sensor node in several applications....
The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing\nfoundry has raised security and privacy concerns with regard to intellectual property (IP) protection\nas well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious\nattacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely\nlogic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur\nconsiderable performance overhead upon the genuine IP design. The focus of this paper is to leverage\nthe unique property of emerging transistor technology on reducing the performance overhead as\nwell as preserving the robustness of logic locking technique. We design the polymorphic logic gate\nusing silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR\n(XOR)-based logic cone. We then evaluate the proposed technique based on security metric and\nperformance overhead....
As technology scales, negative bias temperature instability (NBTI) becomes one of the\nprimary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage\npower increases dramatically as the supply/threshold voltage continues to scale down. These two\nissues pose severe reliability problems for complementary metal oxide semiconductor (CMOS)\ndevices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we\npresent an input vector control (IVC) method based on a linear programming algorithm, which\ncan co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed\nIVC method is combined with the supply voltage assignment technique to further reduce delay\ndegradation and leakage power. Experimental results on various circuits show the effectiveness of\nthe proposed combination method....
Integrated circuits are one of the key complex units available to designers of\nmultichannel detector setups. A whole number of factors makes Application Specific Integrated\nCircuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the\nmost important ones are: integration scale, low power dissipation, radiation tolerance. In order\nto make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs\nshould provide new level of functionality at a new set of constraints and trade-offs, like low-noise\nhigh-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power\ndigitization, fast digital data processing, serialization and data transmission. All integrated\ncircuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not\nreached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies.\nThe paper is based on literary source analysis and presents an overview of the state of the art\nand trends in nowadays chip design, using partially own ASIC lab experience. That shows a\nnext stage of ising micro- and nanoelectronics in physical instrumentation....
Multiplier is one of the essential component in the digital world such as in digital\nsignal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due\nto the complexity of the multiplier, tendency of errors are very high. This paper aimed to design\na 2x2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption\nand high performance. This design have been implemented using 90nm Complemetary Metal\nOxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA)\nTools. Implementation of the multiplier architecture is by using the reversible logic gates. The\nfault tolerance multiplier used the combination of three reversible logic gate which are Double\nFeynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of\n160�¼m x 420.3�¼m (67.25 mm�²). This design achieved a low power consumption of 122.85�¼W\nand propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power\nconsumption and high performance which suitable for application of modern computing as it has\na fault tolerance capabilities....
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